512Mb : x32 TwinDie Mobile SDRAM Addendum
Features
Mobile SDRAM
MT48LC16M32L2 – 4 Meg x 32 x 4 Banks
MT48V16M32L2 – 4 Meg x 32 x 4 Banks
MT48H16M32L2 – 4 Meg x 32 x 4 Banks
Features
Addendum Changes
•
•
•
•
•
•
The standard 256Mb SDRAM Mobile x32 data sheets
should be referenced for a complete description of
SDRAM functionality and operating modes. This
addendum data sheet will concentrate on the key differences required to support the enhanced options of
the TwinDie configuration.
•
•
•
•
•
•
•
•
•
•
Low voltage power supply
Partial array self refresh power-saving mode
Temperature compensated self refresh (TCSR)
Deep power-down mode
Programmable output drive strength
Fully synchronous; all signals registered on positive
edge of system clock
Internal pipelined operation; column address can
be changed every clock cycle
Internal banks for hiding row access/precharge
Programmable burst lengths: 1, 2, 4, 8, or full page
Auto precharge, includes concurrent auto
precharge, and auto refresh modes
Self refresh mode; standard and low power
64ms, 8,192-cycle refresh
LVTTL-compatible inputs and outputs
Operating temperature range
Industrial (-40°C to +85°C)
Supports CAS latency of 1, 2, 3
Options
The Micron 256Mb Mobile X32 data sheet provides full
specifications and functionality unless specified
herein.
Table 1:
• VDD/VDDQ
3.3V/3.3V
2.5V/2.5V
1.8V/1.8V
• Configuration
16M32 stacked die
• Package/ballout
Plastic package 90-ball FBGA
(8mm x 13mm) (standard)
Plastic package 90-ball FBGA
(8mm x 13mm) (lead-free)
• Timing (cycle time)
8ns at CL3 (125 MHz)
10ns at CL3 (100 MHz)
• Temperature
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
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512Mb Mobile SDRAM_TwinDie_x32.fm - Rev. C 6/05 EN
Speed
Grade
Clock
Frequency
-8
-10
125 MHz
100 MHz
Table 2:
Marking
Key Timing Parameters
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
L2
7.5ns
7.5ns
8.5ns
8.5ns
Configuration
Architecture
LC
V
H
Access Time Access Time
at CL = 3
at CL = 2
16 Meg x 32
4 Meg x 32 x 4 banks
8K
8K (A0–A12)
4 (BA0, BA1)
512 (A0–A8)
F5
B5
-8
-10
No Marking
IT
1
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Products and specifications discussed herein are subject to change by Micron without notice.
512Mb : x32 TwinDie Mobile SDRAM Addendum
General Description
General Description
The 512Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing
536,870,912 bits. It is internally configured by stacking two 256Mb, 8 Meg x 32 devices.
Each of these 256Mb devices is configured as a quad bank DRAM with a synchronous
interface. They are organized with 32 DQs with 4 banks of 67,108,864 bits, comprising of
8,192 rows by 512 columns by 32 bits wide.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select
the bank; A0-A12 select the row). The address bits registered coincident with the READ
or WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4, or 8
locations, or the full page, with a burst terminate option. An auto precharge function
may be enabled to provide a self-timed row precharge that is initiated at the end of the
burst sequence.
The 512Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also
allows the column address to be changed on every clock cycle to achieve a high-speed,
fully random access. Precharging one bank while accessing one of the other three banks
will hide the precharge cycles and provide seamless, high-speed, random-access operation.
The 512Mb SDRAM is designed to operate in 3.3V, 2.5V, and 1.8V memory systems. An
auto refresh mode is provided, along with a power-saving, power-down mode. All inputs
and outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time, and the
capability to randomly change column addresses on each clock cycle during a burst
access.
Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering die intitialization, register definition, command
descriptions, and device operation on a per die basis unless otherwise noted.
This addendum documents any variances for the 512Mb: x32 Mobile SDRAM from the
256Mb: x32 Mobile SDRAM specification. Please refer to the 256Mb: x32 Mobile SDRAM
data sheet on Micron’s Web site for additional details on the part functionality.
Commands
AUTO REFRESH
AUTO REFRESH is used during normal operation of the SDRAM and is analogous to
CAS#-BEFORE-RAS# (CBR) REFRESH in conventional DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. All active banks must be
PRECHARGED prior to issuing a AUTO REFRESH command. The AUTO REFRESH command should not be issued until the minimum tRP has been met after the PRECHARGE
command as shown in the operations section.
The addressing is generated by the internal refresh controller. This makes the address
bits “Don’t Care” during an AUTO REFRESH command. The 512Mb TwinDie™ Mobile
SDRAM requires 8,192 AUTO REFRESH cycles every 64ms (tREF). Providing a distributed
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Commands
AUTO REFRESH command every 7.81µs will meet the refresh requirement and ensure
that each row is refreshed. Alternatively, 8,192 AUTO REFRESH commands can be issued
in a burst at the minimum cycle rate (tRC), once every 64ms.
Figure 1:
Functional Block Diagram
CS
CLK
CKE#
TOP
BOTTOM
DIE
DIE
Command
Addresses
DQ0-DQ31
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Ball Assignment
Ball Assignment
Figure 2:
90-Ball FBGA Assignment
1
2
3
DQ26
DQ24
DQ28
4
5
6
7
8
9
VSS
VDD
DQ23
DQ21
VDDQ
VSSQ
VDDQ
VSSQ
DQ19
VSSQ
DQ27
DQ25
DQ22
DQ20
VDDQ
VSSQ
DQ29
DQ30
DQ17
DQ18
VDDQ
VDDQ
DQ31
NC
NC
DQ16
VSSQ
VSS
DQM3
A3
A2
DQM2
VDD
A4
A5
A6
A10
A0
A1
A7
A8
A12
NC
BA1
A11
CLK
CKE
A9
BA0
CS#
RAS#
DQM1
NC
NC
CAS#
WE#
DQM0
VDDQ
DQ8
VSS
VDD
DQ7
VSSQ
VSSQ
DQ10
DQ9
DQ6
DQ5
VDDQ
VSSQ
DQ12
DQ14
DQ1
DQ3
VDDQ
DQ11
VDDQ
VSSQ
VDDQ
VSSQ
DQ4
DQ13
DQ15
VSS
VDD
DQ0
DQ2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
Ball and Array
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Electrical Specifications
Electrical Specifications
Table 3:
DC Electrical Characteristics and Operating Conditions (LC version)
VDD/VDDQ = +3.3V ±0.3V
Notes: 1, 5, 6; please refer to the 256Mb: x32 Mobile SDRAM data sheet for all notes.
Parameter/Condition
Supply Voltage
Input High Voltage: Logic 1; All inputs
Input Low Voltage: Logic 0; All inputs
Input Leakage Current:
Any input 0V ≤ VIN ≤ VDD
(All other balls not under test = 0V)
Output Leakage Current: DQs are disabled; 0V ≤ VOUT ≤
VDDQ
Output Levels:
Symbol
MIN
MAX
Units
Notes
VDD/VDDQ
VIH
VIL
II
3
3.6
0.8 x VDDQ
-0.3
-5
VDD + 0.3
0.3
5
V
V
V
µA
22
22
IOZ
-5
5
µA
VOH
VDDQ - 0.2
–
V
VOL
–
0.2
V
Output High Voltage (IOUT = -4mA)
Output Low Voltage (IOUT = 4mA)
Table 4:
DC Electrical Characteristics and Operating Conditions (V version)
VDD = +2.5V ±0.2V VDDQ = +2.5V ±0.2V or VDDQ = +1.8V ±0.15V
Notes: 1, 5, 6; please refer to the 256Mb: x32 Mobile SDRAM data sheet for all notes.
Parameter/Condition
Supply Voltage
Input High Voltage: Logic 1; All inputs
Input Low Voltage: Logic 0; All inputs
Input Leakage Current:
Any input 0V ≤ VIN ≤ VDD
(All other balls not under test = 0V)
Output Leakage Current: DQs are disabled; 0V ≤ VOUT ≤
VDDQ
Output Levels:
Symbol
MIN
VDD/VDDQ
VIH
VIL
II
2.3
0.8 x VDDQ
-0.3
-3.0
IOZ
Output High Voltage (IOUT = -4mA)
Output Low Voltage (IOUT = 4mA)
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5
MAX
Units
Notes
2.7
0.3
3.0
V
V
V
µA
22
22
-3.0
3.0
µA
VOH
0.9 x VDDQ
–
V
VOL
–
0.2
V
VDDQ + 0.3
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Electrical Specifications
Table 5:
DC Electrical Characteristics and Operating Conditions (H version)
VDD = +1.8V ±0.1V VDDQ = +1.8V ±0.1V
Notes: 1, 5, 6; please refer to the 256Mb: x32 Mobile SDRAM data sheet for all notes.
Parameter/Condition
Supply Voltage
Input High Voltage: Logic 1; All inputs
Input Low Voltage: Logic 0; All inputs
Input Leakage Current:
Any input 0V ≤ VIN ≤ VDD
(All other balls not under test = 0V)
Output Leakage Current: DQs are disabled; 0V ≤ VOUT ≤
VDDQ
Output Levels:
Output High Voltage (IOUT = -4mA)
Output Low Voltage (IOUT = 4mA)
Table 6:
Symbol
MIN
VDD/VDDQ
VIH
1.7
MAX
Units
Notes
1.9
VDDQ + 0.3
V
V
22
VIL
II
0.8 x VDDQ
-0.3
-1.0
0.3
1.0
V
µA
IOZ
-1.5
1.55
µA
VOH
0.9 x VDDQ
–
V
VOL
–
0.2
V
22
IDD Specifications and Conditions (LC version)
VDD = +3.3V ±0.3V, VDDQ = +3.3V ±0.3V
Notes: 1, 5, 6, 11, 13; please refer to the 256Mb: x32 Mobile SDRAM data sheet for all notes.
MAX
Parameter/Condition
Operating Current: Active Mode; Burst = 2; READ or
WRITE;
tRC = tRC (MIN)
Standby Current: Power-Down Mode; All banks idle; CKE
= LOW
Standby Current: Power-Down Mode; All banks idle; CKE
= HIGH
Standby Current: Active Mode; CKE = HIGH; CS# = HIGH;
All banks active after tRCD met; No accesses in progress
Standby Current: Active Mode; CKE = LOW; CS# = HIGH;
All banks active; No accesses in progress
Operating Current: Burst Mode; Continuous burst; READ
or WRITE; All banks active, half DQs toggling every cycle.
tRFC = tRFC
Auto Refresh Current
CKE = HIGH; CS# = HIGH
(MIN)
t
RFC = 7.8µs
Deep power down
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6
Symbol
-8
-10
Units
Notes
IDD1
210
185
mA
3, 18, 19, 28
IDD2N
800
800
µA
32
IDD2NS
60
60
mA
IDD3NS
80
80
mA
IDD3N
60
60
mA
IDD4
165
140
mA
3, 18, 19, 28
IDD5
300
250
mA
3, 12, 18, 19,
28, 29
IDD6
IZZ
5.0
20
5.0
20
mA
µA
3, 12, 19, 28
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512Mb : x32 TwinDie Mobile SDRAM Addendum
Electrical Specifications
Table 7:
IDD Specifications and Conditions (V version)
VDD = +2.5 ±0.2V, VDDQ = +2.5 ±0.2V
Notes: 1, 5, 6, 11, 13; please refer to the 256Mb: x32 Mobile SDRAM data sheet for all notes.
MAX
Parameter/Condition
Symbol
-8
-10
Units
Notes
IDD1
210
185
mA
3, 18, 19, 28
IDD2N
800
800
µA
32
IDD2NS
60
60
mA
IDD3NS
80
80
mA
IDD3N
60
60
mA
IDD4
165
140
mA
3, 18, 19, 28
IDD5
300
250
mA
3, 12, 18, 19,
28, 29
IDD6
IZZ
5.0
20
5.0
20
mA
µA
Operating Current: Active Mode; Burst = 2; READ or
WRITE;
t
RC = tRC (MIN)
Standby Current: Power-Down Mode; All banks idle;
CKE = LOW
Standby Current: Power-Down Mode; All banks idle;
CKE = HIGH
Standby Current: Active Mode; CKE = HIGH; CS# = HIGH;
All banks active after tRCD met; No accesses in progress
Standby Current: Active Mode; CKE = LOW; CS# = HIGH;
All banks active; No accesses in progress
Operating Current: Burst Mode; Continuous burst;
READ or WRITE; All banks active, half DQs toggling
every cycle.
tRFC = tRFC
Auto Refresh Current
CKE = HIGH; CS# = HIGH
(MIN)
tRFC = 7.8µs
Deep power down
Table 8:
3, 12, 19, 28
IDD Specifications and Conditions (H version)
VDD = 1.8 ±0.1V, VDDQ = 1.8V ±0.1V
Notes: 1, 5, 6, 11, 13; please refer to the 256Mb: x32 Mobile SDRAM data sheet for all notes.
MAX
Parameter/Condition
Symbol
-8
-10
Units
Notes
IDD1
155
130
mA
3, 18, 19, 28
IDD2N
600
600
µA
32
IDD2NS
40
40
mA
IDD3NS
60
60
mA
IDD3N
40
40
mA
IDD4
115
95
mA
3, 18, 19, 28
IDD5
245
205
mA
3, 12, 18, 19,
28, 29
IDD6
IZZ
5.0
20
5.0
20
mA
µA
Operating Current: Active Mode; Burst = 2; READ or
WRITE;
tRC = tRC (MIN)
Standby Current: Power-Down Mode; All banks idle;
CKE = LOW
Standby Current: Power-Down Mode; All banks idle;
CKE = HIGH
Standby Current: Active Mode; CKE = HIGH; CS# = HIGH;
All banks active after tRCD met; No accesses in progress
Standby Current: Active Mode; CKE = LOW; CS# = HIGH;
All banks active; No accesses in progress
Operating Current: Burst Mode; Continuous burst;
READ or WRITE; All banks active, half DQs toggling
every cycle.
t
Auto Refresh Current
RFC = tRFC
CKE = HIGH; CS# = HIGH
(MIN)
tRFC = 7.8µs
Deep power down
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3, 12, 19, 28
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IDD7 Curves
Table 9:
IDD7 - Self Refresh Current Options
Note: 4; please refer to the 256Mb: x32 Mobile SDRAM data sheet for all notes. Values for IDD7 for 85ºC are
100 percent tested. Values for 70ºC, 45ºC, and 15ºC are sampled only.
Temperature Compensated Self
Refresh Parameter/Condition
MAX
Temperature
VDD = 3.3
VDD = 2.5
VDD = 1.8
Units
Notes
85ºC
70ºC
45ºC
15ºC
85ºC
70ºC
45ºC
15ºC
85ºC
70ºC
45ºC
15ºC
85ºC
70ºC
45ºC
15ºC
85ºC
70ºC
45ºC
15ºC
1600
1300
1000
864
1200
1025
875
800
1000
900
800
760
900
825
780
750
850
800
760
740
1600
1300
1000
864
1200
1025
875
800
1000
900
800
760
900
825
780
750
850
800
760
740
1200
960
740
630
900
760
640
580
750
660
590
560
680
610
566
540
640
590
550
536
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Self Refresh Current:
CKE = LOW – 4 Bank Refresh
Self Refresh Current:
CKE = LOW – 2 Bank Refresh
Self Refresh Current:
CKE = LOW – 1 Bank Refresh
Self Refresh Current:
CKE = LOW – Half Bank Refresh
Self Refresh Current:
CKE = LOW – Quarter Bank Refresh
IDD7 Curves
Figure 3:
Typical Self Refresh Current vs. Temperature – 3.3V Part
1200
1100
1000
900
Currrent (uA)
800
700
600
500
IDD7-- 4-Bank
IDD7-- 2-Bank
400
IDD7-- 1-Bank
300
IDD7-- 1/2-Bank
200
IDD7-- 1/4-Bank
100
0
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
Temperature (C)
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IDD7 Curves
Figure 4:
Typical Self Refresh Current vs. Temperature – 2.5V Part
1200
1100
1000
900
Currrent (uA)
800
700
600
500
IDD7-- 4-Bank
IDD7-- 2-Bank
400
IDD7-- 1-Bank
300
IDD7-- 1/2-Bank
200
IDD7-- 1/4-Bank
100
0
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
Temperature (C)
Figure 5:
Typical Self Refresh Current vs. Temperature – 1.8V Part
1000
900
800
Currrent (uA)
700
600
500
IDD7-- 4-Bank
400
IDD7-- 2-Bank
300
IDD7-- 1-Bank
IDD7-- 1/2-Bank
200
IDD7-- 1/4-Bank
100
0
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
Temperature (C)
Table 10:
Capacitance
Parameter – FBGA “S2” Package
Input Capacitance: CLK
Input Capacitance: All other input-only balls
Input/Output Capacitance: DQs
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Symbol
MIN
MAX
Units
CI1
CI2
CIO
5
5
8
8
8
12
pF
pF
pF
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Package Dimensions
Package Dimensions
Figure 6:
90-Ball FBGA (8mm x 13mm)
1.00 ±0.05
SEATING
PLANE
SOLDER BALL MATERIAL:
62% Sn, 36% Pb, 2% Ag OR
96.5% Sn, 3%Ag, 0.5% Cu
SOLDER MASK DEFINED
BALL PADS: Ø0.40
C
0.10 C
90X Ø0.45
SOLDER BALL
DIAMETER REFERS
TO POST REFLOW
CONDITION. THE PREREFLOW DIAMETER
IS Ø0.42
SUBSTRATE MATERIAL:
PLASTIC LAMINATE
MOLD COMPOUND:
EPOXY NOVOLAC
6.40
0.80 TYP
BALL A1 ID
BALL A1 ID
BALL A1
BALL A9
0.80 TYP
CL
11.20
13.00 ±0.10
5.60
6.50 ±0.05
CL
3.20
1.40 MAX
4.00 ±0.05
8.00 ±0.10
Notes: 1. All dimensions in millimeters.
2. Recommended pad size for PCB is 0.4mm ±0.025mm.
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range
for production devices. Although considered final, these specifications are subject to change, as further product
development and data characterization sometimes occur.
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